1. Field of the Invention
This invention relates to generating related timing signals that have a minimal time delay or skew with respect to a master clock signal. In particular this invention uses a tri-state buffer driven by the original master clock to lessen the skew between the resulting dependent clock and the master clock signal.
Description of the Prior Art
In the design of digital circuits there is usually a need to synchronize the clocking of many elements to a single master clock source. Many times, it is also necessary to clock a certain portion of the circuit at a rate that is different from, but still dependent on, a master clock source. Such dependencies could include 1/2 or 1/4 the master rate or could be 1/n of the rate shifted by "m" periods of the master rate. The act of cresting such a dependent clock requires the use of flip flops and other logic which can cause a delay from the master clock signals, called a "skew", is sometimes unacceptable, especially in high speed electronic circuits. When the delay is not acceptable, the designer has to resort to other silicon methods to achieve the same logical events. This is commonly done by adding a multiplexer to every instance of logic that required a dependent clock. The multiplexer is activated with a signal that is appropriately related to the original clock. The master clock is usually used as the instance clock. While this system always works, it requires that a significant amount of silicon be added to the circuit.
What is needed, then, is a dependent clock generator that does not incur the delays associated with the logic that is used to create such a signal.